Modern integrated circuits (ICs) are made up of millions or even billions of transistors, where each transistor can switch on and off more than a billion of times per second. These logical operations, which are densely packed both physically and temporally, are what provide modern ICs with sufficient processing power to carry out complex algorithms required in modern communication systems, vehicular systems, industrial systems, and the like.
Although modern manufacturing processes allow engineers to build circuits with these feature densities, the feature densities in combination with the fast operating frequencies can lead to challenges. One such challenge is clock skew, which is sometimes called timing skew. Clock skew is a phenomenon in synchronous circuits where a clock signal (sent from a clock circuit) arrives at different gates at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical, and less variation can be tolerated if the circuit is to function properly.
Thus, clock skew introduces a phase shift or phase difference in the arrival time between two sequentially-adjacent registers. It is desirable to limit clock skew to help ensure logical operations are performed accurately on chip.